library ieee;
use ieee.std_logic_1164.all;

entity ShiftRegister32_tb is
	
end entity ShiftRegister32_tb;

architecture RTL of ShiftRegister32_tb is

	component ShiftRegister32
	
		port (
			clk, clr, load, hold, serialIn : in bit;
			inVec : in bit_vector(31 downto 0);
			outVec : out bit_vector(31 downto 0)
		);
		
	end component;
	
	for all : ShiftRegister32 use entity work.ShiftRegister32(RTL);
	
	signal clk : bit := '0';
	signal clr : bit := '1'; -- active low
	signal load : bit := '0';
	signal hold : bit := '1';
	signal inVec : bit_vector(31 downto 0) :=
	"10000000000000000000000000000000";
	signal outVec : bit_vector(31 downto 0);
	
begin

	clk <= not clk after 50 ns;
	
	SHFT : ShiftRegister32 port map (clk, clr, load, hold,'0', inVec, outVec);
	
	tb : PROCESS
		
	begin
	
	load <= '1';
	hold <= '0';
	
	wait for 60 ns;
	
	load <= '0';
	hold <= '0';
	
	wait for 200 ns;
	
	load <= '0';
	hold <= '1';
		
	wait for 500 ns;
	
	clr <= '0';
	load <= '0';
	hold <= '0';
	
	
	wait;
		
	end PROCESS;
	

end architecture RTL;
